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ltc3602 1 3602fb typical application features applications description 2.5a, 10v, monolithic synchronous step-down regulator the ltc ? 3602 is a high ef? ciency, monolithic synchronous, step-down dc/dc converter utilizing a constant-frequency, current mode architecture. it operates from an input voltage range of 4.5v to 10v and provides an adjustable regulated output voltage from 0.6v to 9.5v while delivering up to 2.5a of output current. the internal synchronous power switch with 65m on-resistance increases ef? ciency and eliminates the need for an external schottky diode. the switching frequency can either be set by an external resistor or synchronized to an external clock. opti-loop ? compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the ltc3602 can be con? gured for either burst mode op- eration or forced continuous operation. forced continuous operation reduces noise and rf interference, while burst mode operation provides the high ef? ciency at light loads. in burst mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. 3.3v, 2.5a, 1mhz step-down regulator n wide input voltage range: 4.5v to 10v n 2.5a output current n low r ds(on) internal switches: 65m and 90m n programmable frequency: 300khz to 3mhz n low quiescent current: 75a n 0.6v 1% reference allows low output voltage n 99% maximum duty cycle n adjustable burst mode ? clamp n synchronizable to external clock n power good output voltage monitor n overtemperature protection n available in 16-lead exposed tssop and 4mm 4mm qfn packages n point-of-load supplies n portable instruments n server backplane power n battery-powered devices ef? ciency and power loss vs load current 105k 3602 ta01 22f 100f 0.22f 2.2h 1f 1nf run r t pgood track/ss i th boost sw pgnd ltc3602 pv in intv cc sync/mode v fb 105k 475k 22pf 4.32k v out 3.3v 2.5a v in 4.5v to 10v , lt, ltc, ltm, burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. load current (a) 0.01 80 efficiency (%) power loss (mw) 90 100 0.1 1 10 3602 ta01b 70 75 85 95 65 60 100 1000 10000 10 1 power loss efficiency v in = 7v
ltc3602 2 3602fb electrical characteristics absolute maximum ratings input supply voltage (pv in ) ....................... ?0.3v to 11v sw (dc) ...................................... ?0.3v to (pv in + 0.3v) boost ................................. (v sw ?0.3v) to (v sw + 6v) run ........................................................... ?0.3v to 11v all other pins ............................................... ?0.3v to 6v (note 1) symbol parameter conditions min typ max units pv in operating voltage range 4.5 10 v v fb regulated feedback voltage i th = 0.7v (note 3) l 0.594 0.6 0.606 v v fb(linereg) feedback voltage line regulation v in = 5v to 10v, i th = 0.7v 0.005 %/v v fb(loadreg) feedback voltage load regulation i th = 0.36v to 0.84v l 0.02 0.1 % fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 sync/mode pgood r t i th v fb run track/ss pgnd intv cc pv in boost sw sw sw pgnd pgnd 17 t jmax = 125c, ja = 38c/w, jc = 10c/w exposed pad (pin 17) is sgnd, must be soldered to pcb 20 19 18 17 16 6 7 8 top view 21 uf package 20-lead (4mm s 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 pv in pv in intv cc sync/mode pgood pgnd pgnd pgnd pgnd track/ss boost sw sw sw sw r t i th v fb sgnd run t jmax = 125c, ja = 37c/w, jc = 10c/w exposed pad (pin 21) is sgnd, must be soldered to pcb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 8.4v unless otherwise speci? ed. peak sw sink and source current (note 7) .............6.5a operating temperature range (note 2)....?40c to 85c junction temperature (notes 5, 6)........................ 125c lead temperature (soldering, fe package 10 seconds) ................. 300c pin configuration lead free finish tape and reel part marking* package description temperature range ltc3602efe#pbf ltc3602efe#trpbf 3602fe 16-lead plastic tssop ?40c to 85c ltc3602ife#pbf ltc3602ife#trpbf 3602fe 16-lead plastic tssop ?40c to 85c ltc3602euf#pbf ltc3602euf#trpbf 3602 20-lead (4mm 4mm) plastic qfn ?40c to 85c ltc3602iuf#pbf ltc3602iuf#trpbf 3602 20-lead (4mm 4mm) plastic qfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information
ltc3602 3 3602fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3602e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc3602 is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). symbol parameter conditions min typ max units v pgood power good range 10 12 % r pgood power good resistance 11 18 i fb fb input bias current 10 na g m transconductance ampli? er g m 1.7 ms i s supply current active mode sleep mode shutdown (note 4) 500 75 0.2 700 100 1 a a a intv cc v cc ldo output voltage 4.8 5 5.2 v t on, min minimum controllable on-time 90 ns v run run pin on threshold v run rising l 0.4 0.7 1 v i track/ss track/ss pull-up current 1.25 a f osc oscillator frequency r t = 105k 0.8 1 1.2 mhz f sync sync capture range 0.3 3 mhz r ds(on) top switch on-resistance bottom switch on-resistance 90 67 m m i lim peak current limit 3.8 4.5 5.2 a i lsw switch leakage current 0.1 1 a v uvlo intv cc undervoltage lockout intv cc ramping up 4.1 4.2 4.3 v v uvlo, hys intv cc undervoltage lockout hysteresis 700 mv electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 8.4v unless otherwise speci? ed. note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient temperature t a and the power dissipation as follows: t j = t a + (p d )( ja c/w). note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: this limit indicates the current density limitations of the internal metallization and it is not tested in production. typical performance characteristics burst mode operation load step transient forced continuous 10s/div output voltage 50mv/div inductor current 500ma/div 3602 g01 v in = 7v v out = 3.3v load = 50ma 10s/div output voltage 100mv/div load current 1a/div 3602 g02 v in = 7v v out = 3.3v
ltc3602 4 3602fb temperature (c) frequency (khz) 995 1000 1005 990 985 980 1010 1015 1020 3602 g09 C50 25 75 C25 0 50 100 125 r osc = 105k input voltage (v) 4 300 400 600 79 200 100 56 8 10 0 500 quiescent current (a) 3602 g10 sleep active temperature (c) 300 400 600 200 100 0 500 quiescent current (a) 3602 g11 C50 25 75 C25 0 50 100 125 sleep active input voltage (v) 4 frequency (khz) 995 1000 1005 7 9 990 985 980 56 8 1010 1015 1020 3602 g08 r osc = 105k temperature (c) C50 v ref (v) 0.6004 0.6006 0.6008 25 75 0.6002 0.6000 C25 0 50 100 125 0.5998 0.5996 v in = 8.4v 3602 g03 input voltage (v) 4 80 85 95 79 75 70 56 8 10 65 60 90 resistance (m) 3602 g04 bottom top v boost C v sw = intv cc temperature (c) C50 80 100 140 25 75 60 40 C25 0 50 100 125 20 0 120 resistance (m) 3602 g05 bottom top v in = 8.4v typical performance characteristics v ref vs temperature switch on-resistance vs input voltage switch on-resistance vs temperature pv in leakage current vs input voltage frequency vs r osc frequency vs input voltage frequency vs temperature quiescent current vs input voltage quiescent current vs temperature input voltage (v) 4 5 6 79 4 3 56 8 10 2 0 1 7 input current (na) 3602 g06 v run = 0v r osc (k) 0 2000 2500 3500 150 250 1500 1000 50 100 200 300 350 500 0 3000 frequency (khz) 3602 g07
ltc3602 5 3602fb burst clamp voltage (v) 0.4 2.0 2.5 0.7 0.9 1.5 1.0 0.5 0.6 0.8 1.0 0.5 0 3.0 peak inductor current (a) 3602 g12 input voltage (v) 4 90 95 79 85 80 56 8 10 75 70 100 efficiency (%) 3602 g16 i load = 2.5a i load = 1a figure 6 circuit load current (a) 0 C0.10 0.00 1.5 2.5 0.5 1 2 3 C0.20 0.10 v out /v out (%) 3602 g18 figure 6 circuit v in = 7v typical performance characteristics minimum peak inductor current vs burst clamp voltage maximum peak inductor current vs duty cycle ef? ciency vs load current, burst mode operation ef? ciency vs load current, forced continuous ef? ciency vs input voltage ef? ciency vs frequency load regulation 5v ldo output voltage vs temperature track/ss current vs temperature duty cycle (%) 0 peak inductor current (a) 3 4 5 80 2 1 0 10 20 30 40 50 60 70 90 100 3602 g13 frequency (khz) 0 84 efficiency (%) 88 92 96 500 1000 2000 1500 2500 100 86 90 94 98 3000 3602 g17 1h 4.7h 2.2h figure 6 circuit v in = 7v i load = 1a temperature ( o c) C50 4.90 ldo output voltage (v) 4.92 4.96 4.98 5.00 5.10 5.04 0 50 75 4.94 5.06 5.08 5.02 C25 25 100 125 3602 g19 temperature ( o c) C50 1.10 track/ss current (a) 1.15 1.25 1.30 1.35 1.40 0 50 75 1.20 C25 25 100 125 3602 g20 load current (a) 0.01 90 efficiency (%) 95 0.1 1 10 85 80 75 70 100 3602 g14 figure 6 circuit v in = 5v v in = 9v load current (a) 0.01 efficiency (%) 0.1 1 10 3602 g15 figure 6 circuit 0 20 40 60 80 100 10 30 50 70 90 v in = 5v v in = 9v
ltc3602 6 3602fb block diagram pin functions sync/mode (pin 1/pin 4): mode select and external clock synchronization input. pgood (pin 2/pin 5): power good output. open-drain logic output that is pulled to ground when the output volt- age is not within 10% of regulation point. r t (pin 3/pin 6): frequency set pin. i th (pin 4/pin 7): error ampli? er compensation point. v fb (pin 5/pin 8): feedback pin. sgnd (pin 17/pin 9, pin 21): signal ground. run (pin 6/pin 10): run control input. this pin may be tied to pv in to enable the chip. track/ss (pin 7/pin 11): tracking input for the controller or optional external soft-start input. this pin allows the start-up of v out to track the external voltage at this pin using an external resistor divider. an external soft-start can be programmed by connecting a capacitor between this pin and ground. leave this pin ? oating to use the internal 1ms soft-start clamp. do not tie this pin to intv cc or to pv in . pgnd (pins 8, 9, 10/pins 12, 13, 14, 15): power ground. sw (pins 11, 12, 13/pins 16, 17, 18, 19): switch node connection to the inductor. boost (pin 14/pin 20): bootstrapped supply to the top side floating gate driver. pv in (pin 15/pins 1,2): power input supply. decouple this pin with a capacitor to pgnd intv cc (pin 16/pin 3): output of internal 5v ldo. exposed pad (pin 17/pin 21): sgnd. exposed pad is signal ground and must be soldered to the pcb. run r t sync/mode boost i th intv cc pv in 3602 bd ldo sw sw pgnd pgnd pgood v fb track/ss logic slope compensation recovery voltage reference 1ms soft-start osillator slope compensation pgnd sw C + + + C + C + C + C + C + C + + C 1a 0.6v 0.54v 0.66v error amplifier burst comparator over-current comparator reverse comparator main i-comparator bclamp sync/mode fe/uf package
ltc3602 7 3602fb operation main control loop the ltc3602 is a monolithic, constant-frequency, current- mode step-down dc/dc converter. during normal opera- tion, the internal top power switch (n-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error ampli? er adjusts the voltage on the i th pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.6v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error ampli? er raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C2.5a for forced continuous mode and 0a for burst mode operation. the operating frequency is externally set by an external resistor connected between the r t pin and ground. the practical switching frequency can range from 300khz to 3mhz. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 7.5%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mosfet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. forced continuous mode connecting the sync/mode pin to intv cc will disable burst mode operation and force continuous current operation. at light loads, forced continuous mode operation is less ef? cient than burst mode operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of a signal band. the output voltage ripple is minimized in this mode. burst mode operation connecting the sync/mode pin to a voltage in the range of 0.42v to 1v enables burst mode operation. in burst mode operation, the internal power mosfets operate intermittently at light loads. this increases ef? ciency by minimizing switching losses. during burst mode opera- tion, the minimum peak inductor current is externally set by the voltage on the sync/mode pin and the voltage on the i th pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the i th pin drops. as the i th voltage falls below 330mv, the burst comparator trips and enables sleep mode. during sleep mode, the top power mosfet is held off and the i th pin is disconnected from the output of the error ampli? er. the majority of the internal circuitry is also turned off to reduce the quiescent current to 75a while the load current is solely supplied by the output capacitor. when the output voltage drops, the i th pin is reconnected to the output of the error ampli? er and the top power mosfet along with all the internal circuitry is switched back on. this process repeats at a rate that is dependent on the load demand. pulse-skipping opera- tion is implemented by connecting the sync/mode pin to ground. this forces the burst clamp level to be at 0v. as the load current decreases, the peak inductor current will be determined by the voltage on the i th pin until the i th voltage drops below 330mv. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output volt- age in regulation. frequency synchronization the internal oscillator of the ltc3602 can be synchronized to an external clock connected to the sync/mode pin. the frequency of the external clock can be in the range of 300khz to 3mhz. for this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. when synchronized, the ltc3602 will operate in pulse- skipping mode.
ltc3602 8 3602fb operation dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the top switch to remain on for more than one cycle until it attempts to stay on continuously. in order to replenish the voltage on the ? oating boost supply capacitor, however, the top switch is forced off and the bottom switch is forced on for approximately 85ns every sixteen clock cycles. this achieves an effective duty cycle that can exceed 99%. the output voltage will then be primarily determined by the input voltage minus the voltage drop across the upper internal n-channel mosfet and the inductor. slope compensation and inductor peak current slope compensation provides stability in constant-fre- quency architectures by preventing subharmonic oscilla- tions at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 30%. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3602, however, slope compensation recovery is implemented to reduce the variation of the maximum inductor peak current (and therefore the maximum available output current) over the range of duty cycles. short-circuit protection when the output is shorted to ground, the inductor cur- rent decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current increases to more than 4.5a, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. overtemperature protection when using the ltc3602 in an application circuit, care must be taken not to exceed any of the ratings speci- ? ed in the absolute maximum ratings section. as an added safeguard, however, the ltc3602 does incorporate an overtemperature shutdown feature. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. after the part has cooled to below 115c, it will restart. voltage tracking and soft-start some microprocessors and dsp chips need two power supplies with different voltage levels. these systems often require voltage sequencing between the core power supply and the i/o power supply. without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processors i/o ports or the i/o ports of a supporting system device such as memory, an fpga or a data converter. to ensure that the i/o loads are not driven until the core voltage is properly biased, tracking of the core supply and the i/o supply voltage is necessary. voltage tracking is enabled by applying a ramp voltage to the track/ss pin. when the voltage on the track pin is below 0.6v, the feedback voltage will regulate to this tracking voltage. when the tracking voltage exceeds 0.6v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. the track/ss pin is also used to implement an external soft-start function. a 1.2a current is sourced from this pin so that an external capacitor may be added to create a smooth ramp. if this ramp is slower than the internal 1ms soft-start, then the output voltage will track this ramp during start up instead. leave this pin ? oating to use the internal 1ms soft-start ramp. do not tie the track/ss pin to intv cc or to pv in .
ltc3602 9 3602fb applications information the basic ltc3602 application circuit is shown on the front page of this data sheet. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge and switching losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3602 is determined by an external resistor that is connected between the r t pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r fhz k osc = 115 10 10 11 .? () ? although frequencies as high as 3mhz are possible, the minimum on-time of the ltc3602 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 90ns. therefore, the minimum duty cycle is equal to 100 ? 90ns ? f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. i l = v out fl ? ? ? ? ? ? ?1? v out v in ? ? ? ? ? ? having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest ef? ciency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ), where i max is the maximum output current. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a speci? ed maximum, the inductor value should be chosen according to the following equation: l = v out f i l(max) ? ? ? ? ? ? ?1? v out v in(max) ? ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. high ef? ciency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of the more expensive ferrite cores. actual core loss is independent of core size for a ? xed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. un- fortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy ma- terials are small and do not radiate energy but generally cost more than powdered iron core inductors with similar
ltc3602 10 3602fb applications information characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated ? eld/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko and sumida. c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoi- dal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by: ii v v v v rms out max out in in out = () ?? ?1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by: v out ? i l ?esr + 1 8 fc out ? ? ? ? ? ? the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coef? cient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signi? cant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.6v ? 1 + r2 r1 ? ? ? ? ? ? the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 1. r2 ltc3602 r1 3602 f01 sgnd v fb v out figure 1. setting the output voltage
ltc3602 11 3602fb applications information burst clamp programming if the voltage on the sync/mode pin is less than intv cc by 1v or more, burst mode operation is enabled. during burst mode operation, the voltage on the sync/mode pin determines the burst clamp level. this level sets the minimum peak inductor current, i burst , for each switching cycle according to the following equation: v i av v burst burst =+ 6 042 / . v burst is the voltage on the sync/mode pin. i burst can be programmed in the range of 0a to 3.5a, which cor- responds to a v burst range of 0.42v to 1v. as the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is therefore greater than the output load current, the voltage on the i th pin will decrease. when the i th voltage drops to 330mv, sleep mode is enabled in which both power mosfets are shut off along with most of the circuitry to minimize power consumption. all circuitry is turned back on and the power mosfets begin switching again when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep time between pulses and the output voltage ripple increases. the burst clamp voltage, v burst , can be set by a resistor divider from the intv cc pin. alternatively, the sync/mode pin may be tied directly to the v fb pin to set v burst = 0.6v (i burst = 1a), or through an additional divider resistor (r3) to set v burst = 0.46v to 0.6v (see figure 2). pulse-skipping, which is a compromise between low output voltage ripple and ef? ciency, can be implemented by con- necting the sync/mode pin to ground. this sets i burst to 0a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator and the lowest output voltage ripple is achieved while still opera- ting discontinuously. during very light output loads, pulse-skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. frequency synchronization the ltc3602s internal oscillator can be synchronized to an external clock signal. during synchronization, the top mosfet turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300khz to 3mhz. synchronization only occurs if the external frequency is greater than the frequency set by the r t resistor. because slope compensation is generated by the oscillators internal ramp, the external frequency should be set 25% higher than the frequency set by the r t resistor to ensure that adequate slope compensation is present. when synchronized, the ltc3602 will operate in pulse-skipping mode. intv cc regulator the ltc3602 features an integrated p-channel low dropout linear regulator (ldo) that supplies power to the intv cc supply pin from the pv in pin. this ldo supply has been designed to deliver up to 35ma of load current for the powering of the internal gate drivers and other internal circuitry. a small external load may also be applied provided that the total current from the intv cc supply does not exceed 35ma. the intv cc pin should be bypassed with no less than a 0.22f ceramic capacitor. a 1f ceramic capacitor is suitable for most applications. r2 r2 ltc3602 r1 sync/mode sgnd intv cc r3 (optional) ltc3602 r1 3602 f02 sync/mode sgnd fb v out v burst = 0.46v to 1v v burst = 0.46v to 0.6v figure 2. programing the burst clamp
ltc3602 12 3602fb applications information topside mosfet driver supply (boost pin) the ltc3602 uses a bootstrapped supply to power the gate of the internal topside mosfet (figure 3). when the topside mosfet is off and the sw pin is low, diode d bst charges capacitor c bst to the voltage on the intv cc sup- ply. in order to turn on the topside mosfet, the voltage on the boost pin is then applied to its gate. as the topside mosfet turns on, the sw pin rises to the pv in voltage and the boost pin rises to pv in + intv cc , thereby keep- ing the mosfet fully enhanced. for most applications, a 0.22f ceramic capacitor is appropriate for c bst . schottky diode d bst should have a reverse breakdown voltage that is greater than pv in(max) . voltage of the converter. to use the default, internal 1ms soft-start ramp, leave the track/ss pin ? oating. do not tie the track/ss pin to intv cc or to pv in . to increase the soft-start time above 1ms, place a cap on the track/ss pin. a 1.2a internal pull-up current will charge this cap, resulting in a soft-start ramp time given by: t ss = c ss ? 0.6 1. 2 a when the ltc3602 detects a fault condition (either undervoltage lockout or overtemperature), the track/ss pin is quickly pulled to ground and the internal soft-start timer is also reset. this ensures an orderly restart when using an external soft-start capacitor. to implement tracking, a resistor divider is placed between an external supply (v x ) and the track/ss pin as shown in figure 5a. this technique can be used to cause v out to ratiometrically track the v x supply (figure 5b), according to the following: v v r r rr rr out x ta a ab ta tb = + + ? for coincident tracking, as shown in figure 5c, (v out = v x during start-up), r ta = r a , r tb = r b note that the 1.2a current that is sourced from the track/ss pin will cause a slight offset in the voltage seen on the track/ss pin and consequently on the v out volt- age during tracking. this v out offset due to the track/ss current is given by: v os,trk = (1.2a) ? r ta r ta r ta + r tb ? r a + r b r a for most applications, this offset is small and has minimal effect on tracking performance. for improved tracking ac- curacy, reduce the parallel impedance of r ta and r tb . 4.7m ltc3602 3602 f04 pv in run ltc3602 3.3v or 5v run figure 4. run pin interfacing d bst ltc3602 c bst 3602 f03 boost sw intv cc c intvcc figure 3. topside mosfet supply run and soft-start/tracking functions the ltc3602 has a low power shutdown mode which is controlled by the run pin. pulling the run pin below 0.7v puts the ltc3602 into a low quiescent current shutdown mode (i q < 1a). when the run pin is greater than 0.7v, the controller is enabled. the run pin can be driven directly from logic as shown in figure 4. soft-start and tracking are implemented by limiting the effective reference voltage as seen by the error ampli? er. ramping up the effective reference into the error amp in turn causes a smooth and controlled ramp on the output
ltc3602 13 3602fb applications information ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in operating current and i 2 r losses. the v in operating current loss dominates the ef? ciency loss at very low load currents whereas the i 2 r loss dominates the ef? ciency loss at medium to high load currents. 1. the v in operating current comprises three components: the dc supply current as given in the electrical char- acteristics, the internal mosfet gate charge currents and the internal topside mosfet transition losses. the mosfet gate charge current results from switching the gate capacitance of the internal power mosfet switches. the gates of these switches are driven from the intv cc supply. each time the gate is switched from high to low to high again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is the current out of intv cc that is typically larger than the dc bias current. in continuous mode, the gate charge current can be approximated by i gatechg = f(9.5nc). since the intv cc voltage is generated from v in by a linear regula- tor, the current that is internally drawn from the intv cc supply can be treated as v in current for the purposes of ef? ciency considerations. transition losses apply only to the internal topside mosfet and become more prominent at higher input voltages. transition losses can be estimated from: transition loss = (1.7) v in 2 ? i o(max) ? (120pf) ? f 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . in continuous mode, the average output current ? owing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current: i 2 r loss = i o 2 (r sw + r l ) other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% of the total power loss. r b ltc3602 r a 3602 f05a track/ss v fb v out r tb r ta v x time (5b) ratiometric tracking v x v out output voltage time 3602 f05b,c (5c) coincident tracking v x v out output voltage figure 5a. using the track/ss pin to track v x
ltc3602 14 3602fb applications information thermal considerations in most applications, the ltc3602 does not dissipate much heat due to its high ef? ciency. but, in applications where the ltc3602 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to prevent the ltc3602 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t r = (p d ) ? ( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the ltc3602 in dropout at an input voltage of 8v, a load current of 2.5a and an ambi- ent temperature of 70c. from the typical performance graph of switch resistance, the r ds(on) of the top switch at 70c is approximately 120m. therefore, power dis- sipated by the part is: p d = (i load 2 )(r ds(on) ) = (2.5a) 2 (120m) = 0.75w for the tssop package, the ja is 38c/w. thus the junc- tion temperature of the regulator is: t j = 70c + (0.75w)(38c/w) = 98.5c which is below the maximum junction temperature of 125c. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ?(esr), where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components and output capacitor shown in the front page application will provide adequate compensation for most applications. design example as a design example, consider using the ltc3602 in an application with the following speci? cations: v in = 8.4v, v out = 3.3v, i out(max) = 2.5a, i out(min) = 100ma, f= 1mhz. because ef? ciency is important at both high and low load current, burst mode operation will be utilized. first, calculate the timing resistor: r mhz kk osc == 115 10 1 10 105 11 .? ? next, calculate the inductor value for about 40% ripple current at maximum v in : l = 3.3v 1mhz () 1a () ? ? ? ? ? ? ? ? ?1? 3.3v 8 .4v ? ? ? ? ? ? = 2h using a 2.2h inductor results in a maximum ripple cur- rent of: i l = 3.3v 1mhz () 2.2h () ? ? ? ? ? ? ? ? ?1? 3.3v 8 .4v ? ? ? ? ? ? = 0.91a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. in this applica- tion, a tantalum capacitor will be used to provide the bulk
ltc3602 15 3602fb applications information capacitance and a ceramic capacitor in parallel to lower the total effective esr. for this design, a 100f ceramic capacitor will be used. c in should be sized for a maximum current rating of: ia v v v v a rms rms == 25 33 8 4 8 4 33 1122 .? . . ? . . ?. decoupling the pv in pin with a 22f ceramic capacitor is adequate for most applications. the output voltage can now be programmed by choosing the values of r1 and r2. chose r1 = 105k and calculate r2 as: r2 = r1 v out 0.6v ?1 ? ? ? ? ? ? ? ? = 472.5k choose a standard value of r2 = 475k. the voltage on the mode pin will be set to 0.6v by tying the mode pin to the fb pin. this will set the burst current equal to ap- proximately 1a. figure 6 shows a complete schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3602. check the following in your layout: 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3602. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small signal nodes. 4. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , intv cc , v out , pgnd, sgnd, or any other dc rail in your system). figure 6. 8.4v to 3.3v, 2.5a regulator at 1mhz, burst mode operation c in 22f v in 8.4v v out 3.3v 2.5a 3602 f06 d1 l1 2.2h r osc 105k r ith 4.32k r1 105k r pg 200k l1: vishay ihlp2525czer2r2mo1 c in : taiyo yuden tmk325bj226mm-t c out: tdk c3225x5roj107m c vcc 1f c ith 1nf c out 100f sync/mode pgood r t i th v fb run track/ss pgnd intv cc pv in boost sw sw sw pgnd pgnd ltc3602 r2 475k c bst 0.22f pgood c fb 22pf
ltc3602 16 3602fb typical applications 1.8v, 2.5a regulator at 1mhz, burst mode operation ef? cinecy vs load current c in 22f v in 5v to 10v v out 1.8v 2.5a 3602 ta02 d1 l1 1h r osc 105k r ith 4.32k r1 105k r3 845k c vcc 1f c ith 1nf sync/mode pgood r t i th v fb run track/ss pgnd intv cc pv in boost sw sw sw pgnd pgnd ltc3602 r pg 200k r4 137k r2 210k c out 100f s 2 c bst 0.22f pgood l1: vishay ihlp2525czer1r0mo1 c in : taiyo yuden tmk325bj226mm-t c out: taiyo yuden amk316bj107ml c fb 22pf load current (a) 0.01 90 efficiency (%) 95 0.1 1 10 85 80 75 70 100 3602 ta02b v in = 5v v in = 10v v in = 8.4v
ltc3602 17 3602fb typical applications 2.5v, 2.5a regulator, synchronized to 1.8mhz c in 22f v in 10v v out 3.3v 2.5a 3602 ta04 d1 l1 1h r osc 47.5k r ith 2.94k r1 105k r pg 200k c vcc 1f c ith 470pf sync/mode pgood r t i th v fb run track/ss pgnd intv cc pv in boost sw sw sw pgnd pgnd ltc3602 r2 475k c out 47f c bst 0.22f pgood l1: vishay ihlp1616aber1r0m01 c in : taiyo yuden emk316bj226ml-t c out: murata grm3icr60j476me19 c fb 10pf c in 22f v in 8.4v v out 2.5v 2.5a 3602 ta05 d1 l1 1h r osc 69.8k r ith 2.94k r1 105k r pg 200k c vcc 1f c ith 470pf sync/mode pgood r t i th v fb run track/ss pgnd intv cc pv in boost sw sw sw pgnd pgnd ltc3602 r2 332k c out 100f c bst 0.22f pgood 1.8mhz ext. clk l1: vishay ihlp2525czer1r0m01 c in : taiyo yuden tmk325bj226mm-t c out: tdk c3225x5roj107m c fb 22pf 3.3v, 2.5a regulator at 2mhz, forced continuous, small size
ltc3602 18 3602fb package description fe16 (ba) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 o C 8 o 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 C 0.30 (.0077 C .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 p 0.05 0.65 bsc 4.50 p 0.10 6.60 p 0.10 1.05 p 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252 ) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ba
ltc3602 19 3602fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 4.00 p 0.10 4.00 p 0.10 note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 20 19 1 2 bottom viewexposed pad 2.00 ref 2.45 p 0.10 0.75 p 0.05 r = 0.115 typ r = 0.05 typ 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf20) qfn 01-07 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 0.25 p 0.05 0.50 bsc 2.00 ref 2.45 p 0.05 3.10 p 0.05 4.50 p 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 s 45 o chamfer 2.45 p 0.10 2.45 p 0.05 uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710 rev a)
ltc3602 20 3602fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0408 rev b ? printed in usa related parts part number description comments ltc1877 600ma (i out ), 550khz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.7v to 10v, v out(min) = 0.8v, i q = 10a, i sd <1a, ms8 package ltc1879 1.2a (i out ), 550khz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 10v, v out(min) = 0.8v, i q = 15a, i sd <1a, ttsop-16 package ltc3404 600ma (i out ), 1.4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a, i sd <1a, ms8 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20a, i sd <1a, thinsot tm package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd <1a, thinsot package ltc3407/ltc3407-2 dual 600ma/810ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, ms10e and 3mm 3mm dfn packages ltc3409 600ma, 2.6mhz, low (v in) synchronous step-down dc/dc converter 95% ef? ciency, v in : 1.6v to 5.5v, i q = 65a, i sd <1a, 3mm 3mm dfn package ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd <1a, ms10 and 3mm 3mm dfn packages ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd <1a, tssop-16e package ltc3413 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% ef? ciency, v in : 2.25v to 5.5v, v out(min) = v ref/2 , i q = 280a, i sd <1a, tssop-16e package ltc3414 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop-20e package ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop-20e package ltc3418 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 380a, i sd <1a, qfn package ltc3430 60v, 2.75a (i out ), 200khz, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 5.5v to 60v, v out(min) = 1.2v, i q = 2.5ma, i sd = 25a, tssop-16e package ltc3441 1.2a (i out ), 1mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out : 2.5v to 5.5v, i q = 25a, i sd <1a, dfn package ltc3533 2a, 2mhz, wide input voltage synchronous buck-boost dc/dc converter 96% ef? ciency, v in : 1.8v to 5.5v, i q = 40a, i sd <1a, 3mm 4mm dfn package ltc3548 400ma/800ma dual synchronous buck-boost dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, ms8e and dfn packages ltc3610 12a, 24v, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4v to 24v, v out(min) = 0.6v, fast transient response, i q = 900a, i sd <15a, 9mm 9mm qfn package ltc3611 10a, 36v, synchronous step-down dc/dc converter v in : 4v to 32v, fast transient response, i q = 900a, i sd <15a, 9mm 9mm qfn package thinsot is a trademark of linear technology corporation.

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